DRAM Main Memory. Main memory is stored in DRAM cells that have much higher storage density. DRAM cells lose their state over time – must be refreshed periodically, hence the name Dynamic. DRAM access suffers from long access time and high energy overhead.
DRAM has been widely adopted to construct main mem-ory for decades. A DRAM cell consists of one capacitor and one access transistor. The cell represents bit ‘1’ or ‘0’ de-pending on if the capacitor is fully charged1or discharged. DRAM supports three types of accesses —read,write, andrefresh. An on-chip memory controller (MC) decom-
CSE 471 Autumn 02 1. Main Memory. • The last level in the cache – main memory hierarchy is the main memory made of DRAM chips • DRAM parameters (memory latency at the DRAM level):
Data in row buffer is called a DRAM row. Often called “page” – do not confuse with virtual memory page. Read gets entire row into the buffer. Block reads always performed out of the row buffer. Reading a whole row, but accessing one block. Similar to reading a cache line, but accessing one word.
Lecture: DRAM Main Memory. • Topics: virtual memory wrap-up, DRAM intro and basics (Section 2.3) TLB and Cache. Is the cache indexed with virtual or physical address? To index with a physical address, we will have to first look up the TLB, then the cache longer access time.
DRAM Main Memory. Main memory is stored in DRAM cells that have much higher storage density. DRAM cells lose their state over time – must be refreshed periodically, hence the name Dynamic. DRAM access suffers from long access time and high energy overhead.
Die-stacked DRAM: Top layers store data. Bottom logic layer stores the various control, access, and interface circuits. Magic: Stacked means high density, so high b/w interposer integration not so expensive. Current Products:
DRAM Main Memory • Main memory is stored in DRAM cells that have much higher storage density • DRAM cells lose their state over time – must be refreshed periodically, hence the name Dynamic • DRAM access suffers from long access time and high energy overhead 11
Transfer Rate Example Problem. Assume we have 32-Mbit DRAM memory with 8 bits simultaneously read and a cycle time 250 ns. How fast can data be moved out of memory (e.g. transfer rate)? 8b*(1/250ns) = 8b*(4x106/s) = 32 Mbps = 4 MBps.
Main Memory. The last level in the cache – main memory hierarchy is the main memory made of DRAM chips DRAM parameters (memory latency at the DRAM level): Access time: time between the read is requested and the desired word arrives. Cycle time: minimum time between requests to memory (cycle time > access time because need for stabilization of ...