The site isn’t tutorial in nature ... If you are adept at Verilog, you are able to jump to any of the exercises that interest you. Some of the later ones do sort of build on each other, but ...

We also like that the tutorial used some of the more interesting features of Vivado like automatic verification. Even if you are experienced with Verilog, there are some good tips here.

SystemVerilog and SystemC are the languages used for verification and hardware modelling. Both have features which are unique to each of them while some features are inherited from C++ language.

SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches. An immediate assertion may ...