GitHub14d
uart-verilog
This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, ...
Design-Reuse21d
System-on-Chip Design using Self-timed Networks-on-Chip
The input is (currently) provided using structural SystmVerilog with annotations indicating the constraints. The primary output is Verilog 1995 compliant structural verilog. A number of other ...