The IP core ... T-COR-31 Demo IP core for Xilinx 7-series FPGA The FPGA IP core T-COR-32 implements the algorithm of automatic tracking of objects in video and calculation of their motion parameters.

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation.

In the previous pair of installments in this series, you built a simple Verilog demonstration consisting of an adder and a few flip flop-based circuits. The simulations work, so now it is time to ...